The data rate of high-speed signal links determines system performance of all kinds of devices, ranging from smart phones to super computers. Generational changes of devices involves the increase of data rates of signal links. One example bottleneck is that most (if not all) signal links depend on an open eye diagram to function correctly. A voltage comparator/slicer determines the received bit value between logic 0 and 1 by comparing the sampled voltage at a certain timing point to a reference voltage.
Thus this mechanism requires the eye diagram be open with a certain amount of margin. There are numerous factors, including jitter, noise, crosstalk, channel bandwidth/filtering, etc. that can shrink the eye diagram. When the eye diagram is closed or the margin is insufficient, the receiver will fail to recover the correct data that are transferred. Currently, various equalization (EQ) schemes are used to improve the eye diagram, including transmitter linear EQ (TXLE), continuous time linear EQ (CTLE), and decision feedback EQ (DFE). These EQ schemes can improve the data rate by some amount but will fail when the degrading factors are too severe or the data rate is further increased.